Field of the Invention
The present invention relates to an MSK modulator, and more particularly to an MSK modulator having an improved reference wave generator.
An example of the structure of a typical, conventional MSK modulator is shown in FIG. 4. This MSK modulator receives dibit baseband digital signals I and Q and clocks (transmission rate clocks) having one half the symbol rate, and outputs a modulation signal.
FIG. 5 is a timing chart of transmission rate clocks, signals I and Q, and a reference wave.
Signals I and Q are inputted to analog multipliers 45 and 46, respectively, and multiplied by reference wave signals. Signals I and Q are NRZ signals, and processed as polar NRZ signals taking a value 1 or -1 by the analog multipliers 45 and 46. Representing the transmission rate of I and Q signals by r.sub.b (bps), signal Q is delaying from I signal by 1/(2r.sub.b) sec.
Transmission rate clocks are inputted to a low-pass filter 41 to eliminate higher harmonics and obtain a sine wave signal having a frequency of f.sub.b (=r.sub.b /2) which is supplied to a phase adjusting circuit 42. The phase adjusting circuit 42 adjusts the phase of the sine wave signal to make the zero-level points of the sine wave signal in phase with the level transition points of signal I. An output from the phase adjusting circuit 42 is called a reference wave having an initial phase 0 (rad), and represented by cos (2.pi.f.sub.b t). An analog phase shifter 43 shifts the phase of the reference wave cos 2.pi.f.sub.b t) which is supplied to the multiplier 46. This signal is called a reference wave having an initial phase -.pi./2 (rad) whose zero-level points are in phase with the level transition points of signal Q.
If the transition points of signals I and Q are in correct phase with the zero-level points of reference waves, signals S.sub.I and S.sub.Q outputted from the multipliers 45 and 46 have continuous waveforms combining positive and negative half-period waves, as shown in FIG. 6A. However, if there is a phase shift of reference waves, signals S.sub.I and S.sub.Q are discontinuous as shown in FIG. 6B, adversely affecting an eye pattern on the receiving side and degrading the fixed deterioration characteristics.
The analog multiplier 45 multiplies signal I by the reference wave signal cos (2.pi.f.sub.b t) to output signal S.sub.I, and the analog multiplier 46 multiplies signal Q by the reference wave signal sin (2.pi.f.sub.b t) to output signal S.sub.Q.
A multiplier 47 multiplies signals S.sub.I by a carrier A cos (Wot+.theta.o), and a multiplier 48 multiplies signal S.sub.Q a carrier signal A sin (Wot+.theta.o) shifted by an analog phase shifter 44. An adder 49 adds together the output signals from the multipliers 47 and 48, and outputs an MSK modulation signal.
Such a conventional MSK modulator described above uses only the analog low-pass filter 41 to obtain reference wave signals from transmission rate clocks.
Transmission rate clocks contain odd-order higher harmonics of the reference wave frequency f.sub.b, so that the frequency characteristics of the filter is required to be steep at its attenuation range as indicated at .alpha. in FIG. 3.
In order to make the frequency characteristics of a filter steep at its attenuation range, the order of the filter is required to be se high. With the high order filter, a change in delay time at the pass band becomes great. If the cut-off frequency changes because of the temperature characteristics of filter elements and the dispersion of element values, the delay time near the cut-off frequency changes greatly.
From the above reasons, the phase adjusting circuit 42 is provided to make the reference wave signals in phase with digital data. However, it is necessary for the adjustment range of this circuit 42 to be made broad as the dispersion of filter elements becomes large. As a result, the phase of the reference wave signals changes with the temperature characteristics of both the phase adjusting circuit and filter.
In view of the above circumstances, a digital circuit arrangement such as shown in FIG. 12 has been proposed.
In FIG. 12, a waveform data circuit 1281 stores waveform data of sine waves and cosine waves. Waveform data is read from the waveform data circuit 1281 in response to a clock supplied at a predetermined timing. The read-out waveform data is converted into an analog signal by a D/A converter 1282 operating in response to a clock supplied at the same predetermined timing. The analog signal is amplified by an operational amplifier 1283, and unnecessary higher harmonics of the analog signal are eliminated by a low-pass filter 1284. Thereafter, the analog signal is supplied to a multiplier 1285 to multiply baseband signal I or Q by cos (.pi.t/2Tb) or sin (.pi.t/2Tb) to obtain signal S.sub.I or S.sub.Q.
In the digital circuit arrangement shown in FIG. 12, clocks for MSK modulation are obtained digitally. However, since analog signals are obtained by using the D/A converter 82, operation amplifier 83, and low-pass filter 84, there is a time delay at this analog circuit portion which delay difficult to be estimated.
A circuit arrangement compensating for such a time delay is known which is shown in FIG. 13. This circuit has a delay circuit 1386 for delaying timing clocks to be supplied to a D/A converter 1382, a latch circuit 1388 for latching a baseband signal I or Q, and a delay circuit 1387 for delaying transmission rate clocks and controlling the latch timing of the latch circuit 1388.
In this circuit arrangement, the timings of baseband signals are delayed by the delay circuit 1387 and latched by the latch circuit 1388, and the conversion timings of the D/A converter 1382 are delayed by the delay circuit 1386, to thereby adjust the phases of baseband signals and reference wave signals.
However, such a circuit arrangement complicates the delay circuits if timings are intended to be finely adjusted.
A general delay circuit has the structure such as shown in FIG. 14. A plurality of fixed delay elements 1401, 1402, 1403, 1404, . . . are connected in cascade. One of the outputs of the fixed delay elements is selected by, and outputted from, a selector 1400 to adjust delay time. A large number of fixed delay elements are required in order to provide fine delay time adjustment, resulting in a complicated circuit and high cost. Furthermore, a large number of fixed delay elements connected in cascade results in a large output load of ICs so that waveforms of clocks are deformed and a delay time cannot be adjusted reliably.